T3: Power-Aware Testing in the Era of IoT
Patrick Girard, LIRMM / CNRS, France
Xiaoqing Wen, Kyushu Institute of Technology, Fukuoka, Japan
Abstract: Managing power consumption of circuits and systems is one of the most important challenges for the semiconductor industry in the era of IoT. Power management techniques are used today to control the power dissipation during functional operation. Since the application of these techniques has profound implications on manufacturing test, power-aware testing has become indispensable for low-power LSIs and IoT devices. This tutorial provides a comprehensive and practical coverage of power-aware testing. Its first part gives the background and discusses power issues during test. The second part provides comprehensive information on structural and algorithmic solutions for alleviating test-power-related problems. The third part outlines low-power design techniques and shows how low-power devices can be tested safely without affecting yield and reliability.
He received a M.Sc. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research Director at CNRS (French National Center for Scientific Research) and works in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) – France. From 2010 to 2014, he was head of this Microelectronics Department. He is co-Director of the International Associated Laboratory « LAFISI » (French-Italian Research Laboratory on Hardware-Software Integrated Systems) created in 2013 by the CNRS and the University of Montpellier with the Politecnico di Torino, Italy. His research interests include all aspects of digital testing and memory testing, with emphasis on critical constraints such as timing and power. Reliability and fault tolerance are also part of his research activities. He has served on numerous conference committees and is the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE). He is also an Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on CAD and the Journal of Electronic Testing – Theory and Applications (JETTA – Springer). He has supervised 37 PhD dissertations and has published 7 books or book chapters, 65 journal papers, and more than 230 conference and symposium papers on these fields. Patrick Girard is a Fellow of IEEE.
He received a B.E. degree from Tsinghua University, China, in 1986, a M.E. degree from Hiroshima University, Japan, in 1990, and a Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was a Lecturer at Akita University, Japan. He was a Visiting Researcher at University of Wisconsin, Madison, USA, from October 1995 to March 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served as its CTO until 2003. In 2004, he joined Kyushu Institute of Technology, Japan, where he is currently a Professor and Chair of Department of Creative Informatics. He is a Co-Chair of the Technical Activity Committee on Power-Aware Testing under the Test Technology Technical Council of the IEEE Computer Society. He is serving as Associate Editors for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems as well as IEEE Transactions on Very Large Scale Integration Systems. He co-authored and co-edited two books: “VLSI Test Principles and Architectures: Design for Testability” and “Power-Aware Testing and “Test Strategies for Low Power Devices”. His research interests include design, test, and diagnosis of integrated circuits. He holds 43 U.S. Patents and 14 Japan Patents. He received the 2008 Society Best Paper Award from the Information Systems Society of Institute of Electronics, Information and Communication Engineers. He is a Fellow of IEEE.