Tutorial T2

T2: Fundamentals and Advances in Power Integrity in High-Speed Low Power Designs

Ram Achar, Carleton University, Ottawa, Ontario
Jai Narayan Tripathi, STMicroelectronics

Abstract: With the increasing demands for lower power consumption, higher signal speeds, decreasing feature sizes, denser designs and multi-function products, power and signal integrity effects have become the dominant factors limiting the performance of modern electronic products. These effects can be diverse, such as ground bounce, cross-talk, electromagnetic interference, etc., and can seriously impact the design performance at all hierarchical levels including integrated circuits, printed circuit boards, multi-chip modules and backplanes.

A robust power network is essential for reliable operation of on-chip and on-board circuits. Voltage variations may lead to reduced noise margins and may increase propagation delays. Reduced noise margins can cause false switching of gates whereas increased delays may lead to timing errors and impede the overall operating speed of the chip. These issues coupled with high-frequency effects are making the modeling, analysis and design of power distribution networks (PDNs) consisting of chip, package and printed circuit boards, extremely challenging. If not considered during the design stage, power integrity effects can cause failed designs. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in low-power high-speed designs.

It is critical for the ISCAS community to be familiar with the related issues and the recent developments so that they can design the next generation circuits and systems to address the power integrity issues in high-speed low-power designs.

This tutorial presents the necessary fundamentals for understanding the multidisciplinary problem of power integrity in high-speed designs while summarizing the recent advances with industrial case studies.

Biographies

Ram Achar

Dr. Achar currently is a professor in the department of electronics engineering at Carleton University in Ottawa, Canada. Prior to joining Carleton university faculty (2000), he served in various capacities in leading research labs, including T. J. Watson Research Center, IBM, New York (1995), Larsen and Toubro Engineers Ltd., Mysore (1992), Central Electronics Engineering Research Institute, Pilani, India (1992) and Indian Institute of Science, Bangalore, India (1990). His research interests include signal/power integrity analysis, EMC/EMI analysis, circuit simulation, parallel and numerical algorithms, microwave/RF algorithms, modeling/simulation methodologies for sustainable and renewable energy, and mixed-domain analysis.

Dr. Achar received the B. Eng. degree in electronics engineering from Bangalore University. He is an Alumni of RVCE during 1985-89. He obtained M. Eng. degree in micro- electronics from Birla Institute of Technology and Science, Pilani, India in 1992 and the Ph.D. degree from Carleton University in 1998.

Dr. Achar has published over 200 peer-reviewed articles in international transactions/conferences, six multimedia books on signal integrity and five chapters in different books. Dr. Achar received several prestigious awards, including Bharat Guarav Award (2014), Carleton university research achievement awards (2010 & 2004), NSERC (Natural Science and Engineering Research Council) doctoral medal (2000), University Medal for the outstanding doctoral work (1998), Strategic Microelectronics Corporation (SMC) Award (1997) and Canadian Microelectronics Corporation (CMC) Award (1996). He was also a co-recipient of the IEEE advanced packaging best transactions paper award (2007) and IEEE T-CPMT best transactions paper award (2013). His students have won numerous best student paper awards in international forums.

Prof. Achar currently serves as the chair of the Distinguished Lecturer program of IEEE EMC Society, as the Distinguished Lecturer of the Electronic Devices society and also as the General Chair for HPCPS-2017. He also severs on the executive/steering/technical-program committees of several leading IEEE international conferences, such as EPEPS, EDAPS, SPI, ASP-DAC, ECTC and ISCAS, etc. and in the technical committees, EDMS (TC-12 of CPMT) and CAD (MTT-1).

Dr. Achar previously (2011, 2012) served as a Distinguished Lecturer (DLP) of the IEEE Circuits and Systems Society (CASS) and as a guest editor of IEEE Transactions on CPMT, for two special issues on “Variability Analysis” and “3D- ICs/Interconnects”. He also served as the General Co-Chair of several premier conferences, including NEMO-2015 (Electromagnetic and Multi-physics based modeling, simulation and optimization for RF, microwave and terahertz applications), IEEE International conference on SIPI-2015 (Signal Integrity and Power Integrity), IEEE international conference on Electrical Performance of Electronic Packages & Systems (EPEPS-2010, 2011) and as International Guest Faculty on the invitation of the Dept. of Information Technology of Govt. of India, under the SMDP-II program.

He is a founding faculty member of the Canada-India Center of Excellence, chair of the joint chapters of CAS/EDS/SSC societies of the IEEE Ottawa Section, and is a consultant for several leading industries focused on high-frequency circuits, systems and tools. Dr. Achar is a practicing professional engineer of Ontario, a Fellow of IEEE and a Fellow of Engineers Institute of Canada.

Dr. Jai Narayan Tripathi

Dr. Jai Narayan Tripathi was born in Gangapur (Bhilwara), Rajasthan, India. He received his Bachelor of Engineering (Electronics & Communication Engineering) in 2007 from M. L. V. T. & Engineering College (an institute of Govt. of Rajasthan), and Master of Technology (Information and Communication Technology) from DA-IICT, Gandhinagar in 2009, followed by Ph.D. (Electrical Engineering) from Indian Institute of Technology Bombay, Mumbai in 2014. He is currently a Technical Leader in STMicroelectronics, India. He has been working on design issues of high speed systems such as serial links, at STMicroelectronics. His areas of interest are signal integrity, power integrity, EMI/EMC, metaheuristic optimization, and RF circuits. Dr. Tripathi has served as a reviewer for many international journals, such as PIER, IEEE TEMC, IEEE TPES, Microelectronics Journal etc., and has been a TPC member for various international conferences. He has served as a Session Co-Chair for the session ‘High-Speed Channels and Interconnects’ in IEEE EDAPS 2015, held at Seoul (Korea). He was a recipient of Young Investigator Training Program (YITP) Research Award by Associazione Di Fondazioni E Di Casse Di Risparmio Spa, Italy in 2016 and 2017, consecutively. He has delivered invited talks in various universities including IIT Bombay, IIT Mandi, IIT BHU, IIIT Delhi etc. He has more than 45 international research publications to his credit. He was a Visiting Scientist at the Politecnico Di Torino, Italy from April 2016 to May 2016 and from May 2017 to June 2017; where he was also a Visiting Postdoctoral Fellow from August 2016 to November 2016.

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