Tutorial PM7

PM7: Examination of non-linearities in Analog-to-Digital/Digital-to-Analog Converters via integrated design and test to meet challenges for future RF systems

Vipul J. Patel, Air Force Research Laboratory
Samantha M. McDonnell, Air Force Research Laboratory
Charles L. A. Cerny, Air Force Research Laboratory

Abstract: As the semiconductor industry progresses towards a potential hard stop of Moore’s Law, the interface between the analog and the digital realms will continue to exist.  System designs will continue to push the digital interface closer and closer to the radio frequency (RF) front end, but it is not likely that will be a complete elimination of components to the analog-to-digital converter (ADC) or from the digital-to-analog converter (DAC) back into the RF environment.  In most cases under the advances of Moore’s Law have been realized as a parallel design implementation which may offer some incremental performance increase, but may not enable reconfigurability or adaptability depending on the application.  Furthermore, the requirement for a spatial and spectral representation of RF emissions are likely to become of even greater importance as new communication bandwidths are made available under the 5G offering.  This is likely to result in creative wave of analog, mixed-signal and digital circuits capable of simultaneous multi-functional (communications, radar, imaging, etc.) operation.  The intent of this tutorial is to identify the relevant characteristic aspects of ADCs and DACs that are likely to be integrated into a multifunctional design addressing future system design challenges.  In addition, pertinent design-to-test validation methodologies will be presented as a means to improve design robustness.


Vipul J. Patel

He (IEEE S’97-M’13-SM’14) received both the B. S. degree in electrical engineering and the M. S. degree in computer engineering from the University of Cincinnati, Cincinnati, OH in 2001 and 2006, respectively.  He was a design and process engineer with Maxim Integrated in Dallas, TX, where he worked on CMOS timing circuit chipsets and sub-micron CMOS process development from 1998 to 2001. Mr. Patel is currently a mixed-signal designer with the Sensors Directorate, Air Force Research Laboratory (AFRL), Wright-Patterson Air Force Base in Dayton, OH.  He is also an AF technical consultant to the Defense Advanced Research Project Agency (DARPA) in Arlington, VA. His research interests are radio frequency and millimeter-wave integrated circuits and systems, high-performance clocking circuits and data converters, reconfigurable radio hardware, and trusted and assured microelectronics. He has authored and co-authored more than 20 conference and refereed journal articles and one book chapter.  He also holds three patents.

Samantha M. McDonnell

She received the B.S. (2008), M.S. (2010), and Ph.D. (2016) degrees in electrical engineering from The Ohio State University, Columbus, OH. She received the SRC Fellowship in 2008, DAGSI fellowship in 2010, and the four-year SMART fellowship in 2011. Her research interests include RF communications, high-speed data converters, reconfigurable circuits/systems, and calibration. Mrs. McDonnell is currently working as a research electronics engineer with the Sensors Directorate, Air Force Research Laboratory (AFRL), Wright-Patterson Air Force Base in Dayton, OH.

Charles L. A. Cerny

He (IEEE M’92 – SM’05) received a B.S. degree in Physics with honors from Syracuse University in 1986, an M.S. degree in Electrical Engineering from Lehigh University in 1988, and completed his Doctorate in Electrical Engineering from the University of South Florida in 1992.  Dr. Cerny is a Principal Electronics Engineer for the Air Force Research Laboratory and is presently the RF Sensing Core Technical Lead in the Multispectral Sensing and Detection Division of the Sensors Directorate at Wright Patterson Air Force Base, Dayton, OH. He oversees a research portfolio which includes the conceptualizing and characterization of innovative RF architectures requiring the integration of novel component/sub-system technologies based in photonics, semiconductors and superconductors in conjunction with complex RF signal processing meeting the needs for military and aerospace communities. He has received 16 career accolades to date including the Association of Old Crows National Research and Development Award, IEEE Harrell Noble Award for Career Achievement in Electron Device Research, Federal Laboratory Consortium Technology Transfer Award, and AF Materiel Command Science and Technology Achievement Award.  He has received funding for independent research projects from AFOSR, DARPA, IARPA, NSA, the AF Life Cycle Management Center and the AF TENCAP Office.  Dr. Cerny has been a primary and/or co-author on 50 publications placed in professional society journals, AF Technical and Defense/Congressional records or reports.  He is also the co-inventor on 7 US Patents for Semiconductor Apparatus or Processes.  Dr. Cerny graduated from Air War College in 2012 and is the current IEEE Dayton Section Chairman.