Tutorial PM3

PM3: Deep Learning and Neuromorphic Computing – Technology, Hardware and Implementation

Hai Li, Duke University, USA
Garrett S. Rose, University of Tennessee, USA
Kaushik Roy, Purdue University, USA

Abstract: As big data processing becomes pervasive and ubiquitous in our lives, the desire for embeddedeverywhere and human-centric information systems calls for an intelligent computing paradigm that is capable of handling large volume of data through massively parallel operations under limited hardware and power resources. This demand, however, is unlikely to be satisfied through the traditional computer systems whose performance is greatly hindered by the increasing performance gap between CPU and memory as well as the fast-growing power consumption. Although we have not yet fully understood the working mechanism of human brains, the part that we have learned in past seventy years already guided us to many remarkable successes in computing applications, e.g., artificial neural network and machine learning. The recently emerged research on “neuromorphic computing”, which stands for hardware acceleration of braininspired computing, has become one of the most active areas in computer engineering. The objective of the tutorial is to give a comprehensive overview on the status of deep learning and neuromorphic computing, with a particular focus on the hardware design and system implementation. The evolution of neural networks and the acceleration on conventional platform as well as the neuromorphic system designs including the approaches based on CMOS and emerging nanotechnologies will be introduced. New applications and challenges raised in deep learning and neuromorphic computing will be discussed.


Kaushik Roy

He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 700 papers in refereed journals and conferences, holds 15 patents, supervised 75 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award (IEEE Charles Doeser award), Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD Vannevar Bush Faculty Fellow Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015, and many best paper awards in international conferences and IEE journals. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay) and Global Foundries visiting Chair at National University of Singapore. He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings – Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.

Garrett S. Rose

He is an Associate Professor in the Department of Electrical Engineering and Computer Science at the University of Tennessee, Knoxville. He received his B.S. degree in computer engineering from Virginia Polytechnic Institute and State University (Virginia Tech) in 2001. He later received his M.S. and Ph.D. degrees in electrical engineering from the University of Virginia, Charlottesville, in 2003 and 2006, respectively. Prior to joining the University of Tennessee, from June 2011 to July 2014, he was with the Air Force Research Laboratory, Information Directorate, Rome, NY. From August 2006 to May 2011, he was an Assistant Professor in the Department of Electrical and Computer Engineering at the Polytechnic Institute of New York University, Brooklyn, NY. Dr. Rose is a member of ACM and IEEE, including IEEE Circuits and Systems Society and IEEE Computer Society. From April 2014 through March 2017 he was an associate editor for IEEE Transactions on Nanotechnology. His research interests include low-power circuits, system-on-chip design, trusted hardware, and developing VLSI design methodologies for novel nanoelectronic technologies.

Prof. Hai (Helen) Li

She is currently Clare Boothe Luce Associate Professor of Electrical and Computer Engineering Department at Duke University, USA. She has authored or co-authored 190+ technical papers published in peer-reviewed journals and conferences. She authored a book entitled Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing (CRC Press, 2011). Her current research interests include memory design and architecture, neuromorphic architecture for brain-inspired computing systems, and architecture/circuit/device cross-layer optimization for low power and high performance. Dr. Li serves as an Associate Editor of TVLSI, TCAD, TODAES, TMSCS, TECS, CEM, and the IET Cyber-Physical Systems: Theory & Applications. She has served as general chair/co-chair for ISVLSI, ICCE, ISQED and GLSVLSI, technical program chair/co-chair for SoCC, ISVLSI, iNIS and GLSVLSI, and technical committee members for over 20 international conference series. Dr. Li is a distinguished member of ACM and a distinguished speaker of ACM (2017-2020).