PM2: Design for Low-Power Internet-of-Things (IoT) Systems
Shuvra S. Bhattacharyya, University of Maryland and Tampere University of Technology
Francesca Palumbo, University of Sassari
Jarmo Takala, Tampere University of Technology
Marilyn Wolf, Georgia Institute of Technology
Abstract: Internet-of-Things (IoT) systems are widely used in applications including industrial control, medical systems, and smart cities. A single IoT system includes huge numbers of sensor nodes. Low-power operation and wireless communication are both critical to simplify installation and operation of these nodes. On-board processing must be used to pre-process data and minimize communication power. This tutorial will discuss these critical issues in IoT system design from a system perspective. Talks will focus on low-power design, application-specific embedded processing, communication system design, and statistical models for communication management.
The tutorial will take a VLSI systems approach: identifying key system requirements and appropriate technologies to satisfy those requirements. The tutorial will enable students to describe the basic organization of an edge/fog/cloud IoT system; understand key technologies for low-power IoT edge/fog device design, including event computation, sleep modes, and embedded cryptography; be able to apply concepts of application-specific processors to IoT device design; be able to customize coarse-grained accelerators for IoT applications; and be able to apply stochastic models to the optimization of IoT wireless communication.
Shuvra S. Bhattacharyya
He is a Professor in the Department of Electrical and Computer Engineering at the University of Maryland, College Park. He holds a joint appointment in the University of Maryland Institute for Advanced Computer Studies (UMIACS). He is also a part time visiting professor in the Department of Pervasive Computing at the Tampere University of Technology, Finland, as part of the Finland Distinguished Professor Programme (FiDiPro). He is an author of six books, and over 250 papers in the areas of signal processing, embedded systems, electronic design automation, wireless communication, and wireless sensor networks. He received the B.S. degree from the University of Wisconsin at Madison, and the Ph.D. degree from the University of California at Berkeley. Dr. Bhattacharyya has previously held industrial positions as a Researcher at the Hitachi America Semiconductor Research Laboratory (San Jose, California), and Compiler Developer at Kuck & Associates (Champaign, Illinois). He has held a visiting research position at the US Air Force Research Laboratory (Rome, New York). Dr. Bhattacharyya is director of the Maryland DSPCAD Research Group. He serves as co-Editor-in-Chief for the Journal of Signal Processing Systems. He has previously served as Associate Editor for the EURASIP Journal on Embedded Systems, Journal of Signal Processing Systems, and IEEE Transactions on Signal Processing Systems, and as Guest Editor for several other journals. Dr. Bhattacharyya has served as Director of Membership Services for the IEEE Signal Processing Society (2010-2012), and Chair of the IEEE Signal Processing Society Technical Committee on Design and Implementation of Signal Processing Systems (2008-2009). He has also served in chairing roles for many technical conferences. Dr. Bhattacharyya is a Fellow of the IEEE “for contributions to design optimization for signal processing.” He has been a Nokia Distinguished Lecturer (Finland) and Fulbright Specialist (Austria and Germany). He has received the NSF Career Award (USA).
She is currently an assistant professor at the University of Sassari, within the Information Engineering unit of the Department of Political Sciences, Communication Sciences and Information Engineering. She received her summa cum laude “Laurea Degree” in Electronic Engineering in 2005 at the University of Cagliari, then attended the Master Advanced in Embedded System Design in 2006 at the Advanced Learning and Research Institute of the University of Lugano before starting her Ph.D. in Electronic and Computer Engineering at the University of Cagliari. Her research focus is related to reconfigurable systems and to code generation tools and design automation strategies for advanced reconfigurable hardware architectures. For her studies in the fields of dataflow-based programming and hardware customization, she received two Best Paper Awards at the Conference on Design and Architectures for Signal and Image Processing, respectively in 2011 and in 2015, with the works entitled “The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer” and “MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation”. Dr. Palumbo serves in several different Technical Committee of international conferences and she is a permanent Steering Committee Member of the ACM Conference on Computing Frontiers and Associate Editor of the Springer Journal of Signal Processing Systems. At the moment, Dr. Palumbo is the scientific coordinator of the CERBERO (ID: 732105) H2020 European Project on Smart Cyber Physical System Design.
He is Professor on Computer Engineering at Tampere University of Technology, Finland. He received his M.Sc. (hons) degree in Electrical Engineering and Dr.Tech. degree in Information Technology from Tampere University of Technology, Tampere, Finland (TUT) in 1987 and 1999, respectively. From 1992 to 1995, he was a Research Scientist at VTT-Automation, Tampere, Finland. Between 1995 and 1996, he was a Senior Research Engineer at Nokia Research Center, Tampere, Finland. From 1996 to 1999, he was a Researcher at TUT. Since 2000, he has been Professor in Computer Engineering at TUT and held positions as Head of Computer Systems Department and Dean of Faculty of Computing and Electrical Engineering of TUT. Dr. Takala is Co-Editor-in-Chief for Springer Journal on Signal Processing Systems. During 2007-2011 he was Associate Editor and Area Editor for IEEE Transactions on Signal Processing. He has served as Associate Editor for EURASIP Journal on Embedded Systems and EURASIP Research Letters in Signal Processing. Dr. Takala has been Program Chair for IEEE Workshop on Signal Processing Systems (2017), IEEE GlobalSIP Symposium on Signal Processing on Graphics Processing Units and Multicores (2015), and IEEE GlobalSIP Symposium on Software Defined and Cognitive Radios (2013). He has organised special sessions on design and implementation on signal processing systems in IEEE Int. Conf. Acoustics Speech and Signal Processing in 2007 and 2014, IEEE International Conference on Computer Design in 2010. During 2012-2013 he was the Chair of IEEE Signal Processing Society’s Design and Implementation of Signal Processing Systems Technical Committee. Dr. Takala is Senior Member of the IEEE. His research interests include circuit techniques, parallel architectures, and design methodologies for digital signal processing systems.
She is Rhesa S. “Ray” Farmer Distinguished Chair in Embedded Computing Systems and Georgia Research Alliance Eminent Scholar at the Georgia Institute of Technology. She received her BS, MS, and PhD in electrical engineering from Stanford University in 1980, 1981, and 1984, respectively. She was with AT&T Bell Laboratories from 1984 to 1989. She was on the faculty of Princeton University from 1989 to 2007. Her research interests include cyberphysical systems, embedded computing, embedded video and computer vision, and VLSI systems. She has received the ASEE Terman Award and IEEE Circuits and Systems Society Education Award. She is a Fellow of the IEEE and ACM and an IEEE Computer Society Golden Core member.