M1: Sampling Point Optimization and Associated Timing Recovery Methods for High Speed SERDES Receivers
Fulvio Spagna, Intel Corporation
Sitaraman V. Iyer, Intel Corporation
Abstract: The objective of this tutorial is to explore some aspects of SerDes Clock and Data Recovery (CDR) design that relate to the selection of the CDR reference sampling point, how this selection governs aspects of the receiver architecture and how it interacts with the overall channel equalization solution. Key to the discussion is the timing function concept by means of which the CDR reference sampling point is established.
The timing functions examined in this tutorial can be classified as belonging to one of two distinct classes: 1T spaced, based on baud rate phase detectors (Mueller-Müller), or 2T, spaced based on Alexander phase detectors. The focus of the tutorial is on high data rate SerDes design where it is usual, due to practical implementation constraints, to consider only the sign of the phase error and not its magnitude and it is restricted to NRZ signaling. The techniques exposed here are however generally applicable and, as a consequence, can be applied to systems where the data rate increase demands the receiver architecture to transition to an A/D based topology or more complex signaling solutions.
He graduated summa cum laude at the University of Naples in ‘Federico II’, Italy in 1983 with a thesis on “Phase Noise in Microwave Oscillators”. Before joining INTEL in October 2001, Fulvio worked on Read Channel circuit development for Hard Disk Drive applications at several companies among which ST Microelectronics, Silicon Systems and Texas Instruments later. Fulvio’s interests lie in Receiver architectures with emphasis on Clock and Data Recovery and Equalization signal processing. Fulvio is a Senior Principal Engineer in Intel Scalable performance Development Group (SDG) working on architecture and analog/mixed signal designs for high speed serial IO interfaces used in Server class CPUs.
Sitaraman V. Iyer
He obtained his B.Tech. in Electrical Engineering from the Indian Institute of Technology, Bombay in 1996 and MS and PhD in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, USA in 1998 and 2003 respectively. Since 2004 he has been at Intel Corporation Santa Clara where he designs high speed SERDES for Intel’s Server class CPUs. His experience span the full spectrum of high speed IO topics ranging from architecture definition, timing recovery and control system algorithms, analog circuit design, modeling and analysis, jitter budgeting, electrical performance verification, electrical and physical layer spec development and post-Si debug. He is particularly interested in all aspects of performance optimization of the high speed designs including timing recovery and adaptive equalization.