Invited Industrial Speakers
Trends in microelectronics and resulting opportunities for personalized medical applications
Starting from an analysis of needs and success factors for the adoption of medical grade body sensing applications, the talk will discuss the critical technical challenges for the microelectronics industry to be successful in such application spaces. Examples for low power analog and digital circuit design, medical analog front end needs, digital system requirements as well as good choices of technology for such applications will be reviewed. Open challenges to move technology, circuits and systems into the direction of enabling even better medical electronics are elaborated based on practical examples. These examples will go along the lines of system level safety and security, energy consumption, comfort, and ease of use (i.e. also for the often elderly end user!) – as well as for the needed application level flexibility for the medical product developer and for the doctor.
Ralf Brederlow started his career at Corporate Research of Infineon Technologies in 1999 working on security aspects of MCUs, and sensor systems for bio-medical applications. In 2006 he joined Texas Instrument in Freising, Germany, being responsible for the research and development of new circuits and technology for TI’s MSP430 ultra-low power microcontrollers. This product family is still considered to be the lowest power MCU in the market and is used in many medical applications. In 2014 he joined Texas Instrument’s Kilby Labs to start a branch of TI’s research division at the Freising site, managing predevelopment for TI in Europe. Ralf Brederlow is a member of VDE, DPG, and a Senior Member of IEEE.
Challenges with Realizing a Dream IOT System. Always ON, Always Sensing, Maintenance-Free Platforms
Always ON always sensing small form factor edge systems for internet of things (IOT) are becoming ubiquitous. Many applications require these tiny devices to be self-powered and maintenance free. Hence they should be able to harvest energy from available ambient sources and should have low manufacturing cost. Millimeter-scale form factor systems have been developed in academia for the past few years. They are also becoming commercially available. IOT edge systems are essential in today’s cyber physical world. We will introduce the available market and the trends driving this growth in IOT system deployments. That will be followed by typical system requirements for a dream IOT system. We present the requirements for such systems and the challenges associated with realizing them. We add details of two IOT edge systems that followed two distinct system design approaches, namely, bottom-up and top-down.
Tanay Karnik is a Principal Engineer in Microarchitecture Research Lab of Intel Labs. Previously he was the Director of Intel’s University Research Office. He received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign and joined Intel Corporation in 1995. His research interests are in the areas of small form factor systems, 3D architectures, variation tolerance, power delivery and architectures for novel devices. He has published over 80 technical papers, has 74 issued and 40 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several keynotes, invited talks and tutorials, and has served on 7 PhD students’ committees. He was a member of ISSCC, DAC, ICCAD, ICICDT, ISVLSI, ISCAS, 3DIC and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay was General Chair of ISLPED’14, ASQED’10, ISQED’09, ISQED’08 and ICICDT’08. Tanay is an IEEE Fellow, an ISQED Fellow, an Associate Editor for TVLSI, a Senior Advisory Board Member of JETCAS and was a Guest Editor for JSSC.
Hendrik F. Hamann
Technologies for the Internet of Things
One of the most exciting trends in technology is the emergence of the Internet of Things (IoT), which promises great efficiency improvements in literally every industry. In fact, it is believed that the growth of IoT data which comes from sensors, devices, machines etc placed in the (real) physical world, is becoming much larger than the one of social and computer generated data. In this talk we will highlight these unique opportunities and present specific examples where enabling sensing technologies and devices combined with physics-driven analytics has led to novel IoT applications in various industries ranging from active energy management and optimization, environmental sensing and controls, precision agriculture to renewable energy forecasting.
Dr. Hendrik F. Hamann is currently a Senior Manager and Distinguished Researcher in the Physical Sciences Department at the IBM T.J. Watson Research Center, Yorktown Heights, NY. He received his PhD from the University of Göttingen in Germany in 1995. After that, he joined JILA (Joint institute between the University of Colorado and NIST) as a Research Associate in Boulder, Colorado, where he developed novel near-field optical microscopes to study single molecules at high spatial resolution. In 1999 he joined IBM Research at the T.J. Watson Research Center, where he demonstrated for the first time magnetic recording via thermal near-field coupling. Since 2001 he is leading the Physical Analytics program in IBM Research, currently as a Senior Research Manager. Physical Analytics is a term, which IBM coined to describe the emerging field at the intersection of big IoT data, physical modeling and data analytics, which aims providing the underlying intelligence for future and smarter IoT applications (“cognitive IoT”). Between 2005 and 2009 he worked on energy and thermal management all the way from the device level to large scale computing systems. He invented a new technique to measure power distributions of chips under full operations. This method is today extensively used for IBM’s high performance microprocessor design. More recently Hamann’s main accomplishments are IBM’s Measurement and Management Technologies (MMT) for improving energy efficiency of data centers. Hamann’s current research interest includes sensor networks, sensor-based physical modeling, renewable energy, energy management, precision agriculture, system physics and big data technologies. Foremost he has been leading an effort to develop a platform for big spatio-temporal data and analytics. Since 2016 he is a senior manager in IBM Research leading the world-wide activities in IoT research.
Methods and Techniques for Improving Reliability for Automotive IC Designs
Building automotive ICs demand high-reliability design practices. Both early lifetime escapes, measured in Defective Parts per Million (DPPM) and wear-out induced Failures in Time (FIT) are critical design parameters and require different approaches. EDA tools are just evolving which can measure failure and defect rates at the single-digit or below DPPM/FIT rates. Design techniques are critical to achieving this quality of design. In this talk we will discuss some of these techniques and ideas which lead to highly reliability and high quality designs.
Anthony Hill is a Texas Instruments Fellow and Director of Technology Backplane for TI’s Processors Business. His team has broad responsibilities including technology assessment and procurement, analog design, high-performance IP development and validation, and development of design implementation and signoff methodologies. Currently he is working on technology backplane development for automotive and industrial SOCs for TI’s Jacinto™ and Sitara™ products. He joined TI in 1996 after taking his BSEE from Oklahoma State University in 1992, and MSEE and PhD from the University of Illinois Urbana-Champaign in 1993 and 1996. He has been with TI since 1996 and was elected Senior Member of Technical Staff in 2001, Distinguished Member of Technical Staff in 2007, and Fellow in 2016. He has been involved in 8 generations of cutting-edge devices from 180nm to 16nm with TI’s DSP and Processor business groups. He has been at the forefront of applying and driving EDA technologies including SI-based timing, multi-scenario signoff, and physical synthesis. He has been involved and driven numerous patents and publications in areas such as standard cell architecture and design, synthesis, place and route, timing signoff, and reliability.
CMOS-based technology for advanced electrophysiological imaging of neural activity
Multi Electrode Arrays (MEAs) are a standard technology for in-vitro electrophysiology of neuronal networks and brain tissues. Conventional MEAs produced with micro-machined fabrication provide tens of micrometer electrodes at few hundreds micrometer distance thus allowing a limited capability in sensing large networks composed by thousands of cells. Several approaches based on microelectronic and CMOS design have been proposed to integrate thousands of sensing/actuating elements at few micrometer distances. The Active-Pixel Sensor approach has been used to develop a CMOS-MEA providing 4096 electrodes sampled simultaneously at 18KHz per channel. Each square electrode of 21 µm side and 42 (or 81) µm pitch integrates an amplifier beneath the sensing area, thus allowing outstanding signal to noise ratio. Dimension and distance of electrodes of this high-density device, allow to record neuronal electrical activity at cellular resolution covering an area of 2.7 by 2.7 mm (up to 5 by 5 mm in case of 81 µm pitch), introducing for the first time in the MEA field the concept of electrophysiological imaging. Such CMOS-MEAs nowadays are designed, produced and commercialized by 3Brain AG a Swiss company first in the world in providing a complete HW/SW solution based on high-density MEA (HDMEA) for in-vitro electrophysiology applications. In this talk we will first introduce the HD-MEA technology concepts and then we will give you an overview of the experimental contexts in which they are used by several labs worldwide working in the neuroscience field. In particular we will explore the sensing/actuating capabilities of the chip in relation to different biological models ranging from dissociated 2D neuronal cultures to structured brain tissues as acute slices or explanted retinas.
Challenges and Opportunities on the Road to Achieving 10x Effective Processing Rate on Stored Data
Our recent research indicates that certain workloads with lightweight computation against very large data sets could benefit from bringing intelligence closer to flash. We anticipate that for sequential Very Read Intensive (VRI) workloads, these benefits could be in the range of 10x higher effective processing rate, 60-80% power savings, and 20-40% lower TCO at system level. Our new intelligent platforms will progressively integrate logic and processing elements ever closer to the bits.We will be including highly configurable and targetable logic and processing elements, agnostic to attach point and form factor at first. We will partner extensively with leading technology companies up the stack to offer a complete solution, and continue to engage in sustained ecosystem enablement activities. This talk will focus on our blueprint for 10x acceleration
Pankaj Mehra is Vice President of Memory Pathfinding at Samsung Semiconductor. He was previously VP and Senior Fellow at SanDisk and Western Digital. He was SVP and WW CTO of Fusion-io, and before that SVP and CTO of Whodini. A Distinguished Technologist at Hewlett-Packard since 2004, Pankaj was also the founding Chief Scientist of HP Labs in Russia. He held visiting and faculty positions at IBM, UC Santa Cruz, and IIT Delhi in India. Pankaj is a sought-after keynote speaker, an author of three books, and has more than 50 publications and patents. He holds Ph.D. in Computer Science from University of Illinois.
Cadence Design Systems
Approaches for Improving the Failure Rate Analysis for Automotive IC Designs across the Product Lifecycle
Designing for automotive applications requires re-thinking the approach of the analog IC design methodology. Automotive applications place additional requirements on designers, and they need tools to enable design across the product’s lifecycle. The bathtub curve has traditionally been used to describe the failure rates at each phase of the product’s life. Designers need to analyze and reduce the sources of failures during each phase. During the infant mortality phase, it is important to analyze why there are test escapes, bad parts that were not eliminated by manufacturing test. During normal operation, temperature overstress is a key source of failures, and designers need to analyze the effect of temperature on the circuit. Finally, the circuit wear-out phase of a product’s lifecycle needs to be delayed by analyzing the effect of stress on circuit performance to improve circuit reliability. We will discuss how these new challenges can be overcome.