Tutorial AM7

From Emerging Applications, the Quest for Asynchronous Circuits snd Systems

Davide Bertozzi, University of Ferrara
Steven M. Nowick, Columbia University
Milos Krstic, Univ. of Potsdam, IHP Microelectronics
Giacomo Indiveri, University of Zurich
Jean‐Frédéric Christmann, CEA‐LETI
Andrey Mokhov, Newcastle University
Jens Sparsø, DTU, Denmark

Abstract: In the past decade or so asynchronous design has experienced a tremendous surge of interest, as designers grapple with the challenges of deep submicron technology and large‐scale heterogeneous system integration. In a landscape almost entirely dominated by synchronous design, the relentless concern of asynchronous design researchers has always been to make compelling cases for their circuit and system solutions. This concern has shaped the vast majority of previous tutorials on asynchronous design: the goal was to document superior quality metrics with respect to synchronous counterparts. More recently, the onset of emerging applications featuring radical shifts from traditional von Neumann architectures, and/or novel interfacing requirements and/or more advanced power management strategies is changing the concern of researchers. In fact, emerging application requirements indicate the need for some level of asynchrony for efficient system design and/or operation from the ground up, not as an afterthought. For the first time, this tutorial takes the path from emerging applications and system architectures to ad‐hoc asynchronous circuits and systems for them, thus enabling ISCAS attendees to stay technically up‐to‐date about an enabling circuit and system technology for many of the displayed conference innovation themes (internet of things, cognitive computing, smart systems for automotive, etc.). The basic principles as well as the applicability frontiers of asynchronous design will be brought to ISCAS attendees by selected leading experts in the field, with expertise not only on asynchronous design, but also on a specific emerging application/system architecture that is inherently demanding for some level of asynchrony.


Davide Bertozzi

He got his PhD in Electrical Engineering and Computer Science from University of Bologna in 2003. Since 2004 he holds an Assistant Professor position at University of Ferrara, where he is the principal investigator of the MPSoC Research Group. He has been visiting researcher at international academic institutions (Stanford University) and large semiconductor companies (NEC America Labs, NXP Semiconductors, STMicroelectronics, Samsung Electronics). By building on his core expertise on all aspects of on-chip communication, his current research interests span from interconnect-centric heterogeneous parallel computing architectures to design automation for emerging interconnect technologies. He has been involved either as technical leader or principal investigator in research initiatives funded by the European Union (FP7 Galaxy, NaNoC and vIrtical projects) and by the Italian Government (national program for young talented researchers “FIRB 2008”). He is a member of the Hipeac Network-of-Excellence. He has published more than 150 scientific contributions, including conference proceedings, journal papers and book chapters, and has co-edited a book on networks-on-chip for CRC Press in 2010. He received four best paper awards (NOCS 2016, NOCS 2010, MCSoC 2012, SAMOS 2012), three best paper award nominations (DAC 2006, DATE 2013, ASYNC 2015), and a high-impact paper award for one of the most-cited papers ever submitted to ICCD in 30 years. Bertozzi currently holds two national habilitations for full professorship in both computer science and electrical engineering.

Steven M. Nowick

He is a Professor of Computer Science at Columbia University, and former chair and co-founder of the Computer Engineering Program. He is currently the chair of the Frontiers in Computing Systems working group under Columbia’s Data Science Institute. He received a Ph.D. in Computer Science from Stanford University, and a B.A. from Yale University. His main research is on design methodologies and CAD tools for synthesis and optimization of asynchronous and GALS digital systems. His current interests include: scalable and low-latency on-chip interconnection networks for shared-memory parallel processors and embedded systems, extreme low-energy digital systems, neuromorphic computing, hardware accelerators, and variation-tolerant global communication.

Dr. Nowick is an IEEE Fellow, and recipient of an Alfred P. Sloan Research Fellowship, and NSF CAREER and RIA Awards. He received Best Paper Awards at the IEEE International Conference on Computer Design (1991, 2012) and the IEEE Async Symposium (2000). He co-founded the IEEE Async Symposia series, and was Program and General Co-Chair. He was Program Chair of the IEEE/ACM International Workshop on Logic and Synthesis, and program track/subcommittee chair at DAC, DATE and ICCD conferences. He is on the editorial boards of IEEE Design & Test Magazine and ACM Journal on Emerging Technologies in Computer Systems, and formerly on the editorial board of IEEE Transactions on VLSI Systems and Transactions on Computer-Aided Design. He was selection committee chair of the ACM/SIGDA Outstanding Dissertation in Electronic Design Automation Award, and a member of the best paper award committees of DAC and ICCAD conferences. He also received the Columbia Engineering School Alumni Distinguished Faculty Teaching Award. He holds 13 issued US patents.

Milos Krstic

He is a professor for Design- and Test Methodology at the University of Potsdam, Germany. He received his Dr.-Ing. in electronics from Brandenburg University of Technology, Cottbus, Germany in 2006. Since 2001 he has been with IHP Microelectronics, Frankfurt (Oder), Germany, where he is currently a Team leader for design and test methods in the Wireless Communication Systems Department. Prof. Krstić was manager of many European and national R&D projects. He published more than 100 publications and 8 patent applications including GALS and asynchronous design.  He is Program Chair for the ASYNC 2018 Conference, the premier forum for researchers in asynchronous design.

Giacomo Indiveri

He is a Professor at the Faculty of Science of the University of Zurich, Switzerland, and director of the Institute of Neuroinformatics of the University of Zurich and ETH Zurich. He obtained an M.Sc. degree in electrical engineering and a Ph.D. degree in computer science from University of Genoa, Italy. He was a post-doctoral research fellow in the Division of Biology at Caltech and at the Institute of Neuroinformatics of the University of Zurich and ETH Zurich. He holds a “habilitation” in Neuromorphic Engineering at the ETH Zurich Department of Information Technology and Electrical Engineering. He was awarded an ERC Starting Grant on “Neuromorphic processors” in 2011 and an ERC Consolidator Grant on neuromorphic cognitive agents in 2016. His research interests lie in the study of neural computation, with a particular focus on spike-based learning and selective attention mechanisms. His research and development activities focus on the full custom hardware implementation of real-time sensory-motor systems using analog/digital neuromorphic circuits and emerging VLSI technologies.

Andrey Mokhov

He is a Senior Lecturer and Royal Society Industry Fellow at the School of Engineering, Newcastle University, UK. He has been doing research in asynchronous circuits since 2005 when he joined Newcastle University as a PhD student. Since then he published 15 journal articles and more than 30 conference publications in the areas of design and verification of asynchronous systems. His current research is focused on developing mathematical foundations for asynchronous systems and investigating how recent advances in programming languages theory can be applied in the domain of circuit design and formal verification.

Jens Sparsø

He (IEEE member) is a Professor in the Department of Applied Mathematics and Computer Science, Technical University of Denmark. His research interests include: digital circuits and systems, asynchronous circuits, many-core architectures and networks-on-chip – in short, hardware platforms for embedded and cyber-physical systems. He has published more than 90 refereed journal and conference papers and is co-author of the book “Principles of Asynchronous Circuit Design – A Systems Perspective” (Kluwer, 2001). It has become the standard textbook on the topic, and in 2006 it was translated into Chinese at the initiative of the Chinese Academy of Sciences. He received the Radio-Parts Award and the Reinholdt W. Jorck Award in 1992 and 2003 respectively, in recognition of his research on integrated circuits and systems. He received the best paper award at ASYNC 2005, and one of his papers was selected as one of the 30 most influential papers of 10 years of the DATE conference.  He has supervised 16 PhD students.  He is a member of the steering committees the ACM/IEEE Intl. Symposium on Networks-on-Chip (NOCS) and he has been program chair and/or general chair for several conferences including PATMOS, ASYNC and NOCS.