Tutorial AM6

Error-Correcting Decoder Design for Next-Generation Memories: From Theory to Practice

Xinmiao Zhang, The Ohio State University
Hsie-Chia Chang, National Chiao Tung University

Abstract: Memory and storage systems are the backbone of big data analytics, cloud computing, data virtualization, and many other pervasive applications. Error-correcting codes (ECCs) are essential to the reliability of memories, and their implementation largely affects the performance and cost of the overall memory system. This half-day tutorial addresses the hardware architecture design and implementation of error-correcting coding schemes for newer and next-generation memories, from Flash and storage class memories (SCMs) to distributed storage. The involved theories and algorithms are briefly reviewed. Then extensive discussions are given to the VLSI architectures of different codes and schemes achieving tradeoffs on correction capability, silicon area, throughput, latency, and locality. This tutorial provides a systematic introduction of the performance and implementation architectures of ECC schemes to researchers, system designers and hardware engineers interested in memory system design.


Xinmiao Zhang

He received her Ph.D. degree in Electrical Engineering from the University of Minnesota, Twin Cities. She was a Timothy E. and Allison L. Schroeder Assistant Professor 20052010 and Associate Professor 2010-2013 at Case Western Reserve University. She has been with Western Digital/SanDisk 2013-2017, and joined The Ohio State University in 2017 as an Associate Professor.

Dr. Zhang’s research spans the areas of VLSI architecture design, digital storage and communications, security, and signal processing. She published more than 70 papers on VLSI architectures for Reed-Solomon, BCH, and low-density parity-check (LDPC) encoders and decoders. These error-correcting codes are used in almost every modern digital communication and storage system, such as Flash memories, distributed storage, and 5G networks. She also authored the book “VLSI Architectures for Modern Error-Correcting Codes” (CRC 2015). At Western Digital/SanDisk, she continued her research on these topics, and contributed to the development and optimization of error-correcting coding schemes and implementations for the company’s newest state-of-the-art products.

Dr. Zhang received an NSF CAREER Award in January 2009. She is also the recipient of the Best Paper Award at 2004 ACM Great Lakes Symposium on VLSI (GLSVLSI) and 2016 International SanDisk Technology Conference. Dr. Zhang has been a member of the CASS Circuits and Systems for Communications (CASCOM) Technical Committee since 2007 and VLSI Systems and Applications (VSA) Technical Committee since 2006. She served on the committees of many conferences, such as ISCAS, GLSVLSI, SiPS, NVMW, GLOBECOM, and ICC. She has been an associate editor for TCAS-I since 2010, and was a recipient of the CASS Best Associate Editor Award in 2013.

Hsie-Chia Chang

He received the B.S., M.S., and Ph.D. degrees from the Electronics Engineering Department, National Chiao Tung University, Hsinchu, Taiwan, in 1995, 1997, and 2002, respectively.  He was with OSP/DE1, MediaTek Corporation, from 2002 to 2003, where he was involved in decoding architectures for combo single chip.  In 2003, he joined the Electronics Engineering Department, National Chiao-Tung University, as a Faculty Member, where he has been a Professor since 2010.

Dr. Chang’s research interests include algorithms and VLSI architectures in signal processing, in particular, error control codes and crypto-systems.  He also committed himself to designing high code-rate ECC schemes for Flash memory, PUF implementation for secure MCU system, and multi-Gb/s chip implementations for wireless communications.  In addition to authoring over 100 IEEE journal/conference papers and 50 U.S./Taiwan patents, Dr. Chang served as the consultants for MaxNova Inc., Macronix Inc., and Lite-On IT Inc.  Since February 2006, Dr. Change leads the OCEAN (OverCome Error And Noise) group to complete 16 technology transfer cases, mainly targeted on Reed-Solomon, BCH, LDPC codec architectures.

Dr. Chang was a recipient of the Outstanding Youth Electrical Engineer Award from the Chinese Institute of Electrical Engineering in 2010, and the Outstanding Youth Researcher Award from the Taiwan IC Design Society in 2011.  He has served as the Deputy Director General with the Chip Implementation Center, Taiwan, during 2014 to 2017.  He has been an Associate Editor of the IEEE T-CAS I since 2012.  He served as a Technical Program Committee Member of the IEEE Asian Solid-State Circuits Conference (A-SSCC), from 2011 to 2013, and International Solid-State Circuits Conference (ISSCC) in 2018.