Automotive Systems IP and Design Methods
Thomas Wong, Cadence Design Systems
Alessandra Nardi, Cadence Design Systems
Antonino Armato, Cadence Design Systems
Anthony Hill, Texas Instruments
Abstract: In the last decade, the semiconductor industry driven by the automotive market is profoundly influenced by ADAS (Advanced Driver Assistance Systems) and, more recently, by the race to autonomous driving. This tutorial covers the requirements of the automotive market in terms of systems, IP and design methods.
In the first part, we will examine the requirements for ADAS chips and their relationships to highly integrated SOC for autonomous driving. We will highlight the key IPs that are needed and the type of applications they support. We will examine the industry and technology trends and project how these IP requirements will evolve over the next several years as the industry protocol evolves and any ancillary chips become commercially viable (low power memory, low power DSP, neural network processors and cost effective GPU for AI). We will also explore the requirements of NoC Interconnect Fabric IP and its impact on SoC Power, Performance and Area.
The second and third part will focus on the methodology requirements to guarantee the reliability and functional safety metrics. We will provide the foundation of safety methodologies and design principles to perform an effective safety analysis and to develop a robust circuit per the ISO26262 standard. The tutorial will connect Functional Safety to the traditional hardware design and verification flow and will also include an example of FMEDA (Failure Modes Effects and Diagnostic Analysis) performed on a Tensilica vision processor.
The last part will address the high-reliability needs of safety critical applications: these might pose an additional challenge with the advanced technologies, which are in turns needed to fulfill the high-processing power required for autonomous driving. We will start from describing the failure mechanisms and how they are specifically analyzed and addressed in automotive.
Thomas Wong, Director of Business Development, IP Group, Cadence Design Systems
He is Director of Business Development at Cadence Design Systems responsible for foundry, automotive and vertical markets. Tom is an industry veteran with over 25 years’ experience in semiconductor design, IP, DFM and lithography, foundry process, packaging as well as consumer product designs including smartphones and tablets. Tom is an IEEE Senior Member and a (SGS-TUV SC-AFSP) Semiconductor Automotive Functional Safety Professional. Tom received his BSEE and MSEE from University of Wisconsin – Madison
Alessandra Nardi, Software Engineering Group Director, Automotive Solutions, Cadence Design Systems
She is a Software Engineering Group Director at Cadence Design Systems. She holds a Ph.D. in Electrical Engineering from the University of Padova, Italy. After her postdoc at the University of California, Berkeley, she held R&D lead positions in Magma Design Automation, Synopsys and Cadence Design Systems spanning Statistical Static Timing Analysis, Library Characterization and Power Integrity. In the automotive solutions team, Alessandra is currently driving R&D design methodologies for automotive applications, focusing on functional safety and reliability. She gained the Functional Safety Engineer Certification from TUV-SUD.
Antonino Armato, Principal Product Engineer, Automotive Solutions, Cadence Design Systems
He is a Functional Safety Principal Product Engineer at Cadence Design Systems. Based in Milan, Italy, he is involved in many projects related to the functional safety. In the past, Armato joined in Intel 2016 with the acquisition of Yogitech S.p.A as Functional Safety Solution Architect where he has been involved on the safety analysis of System On Chips for automotive application and Software Test Library for Microprocessors. As Yogitech’s functional safety engineer, he has been involved since 2011 on research activities related to the fault tolerance in integrated circuits and on European Project on the design of future reliable SOC. He has worked on the development of many functional safety products related to complex hardware safety mechanisms likes Dual Core Lock-Step (DCLS) architectures, and Software Test Libraries for ARM cores and MCUs. Armato earned a master’s degree in electronic engineering and a Ph.D. in Automatic, Robotic and Bioengineering, respectively from the University of Messina and the University of Pisa, in Italy.
Anthony Hill, TI Fellow, Director of Processors Technology Backplane, Texas Instruments
He is a Texas Instruments Fellow and Director of Technology Backplane for TI’s Processors Business. His team has broad responsibilities including technology assessment and procurement, analog design, high-performance IP development and validation, and development of design implementation and signoff methodologies. Currently he is working on technology backplane development for automotive and industrial SOCs for TI’s Jacinto™ and Sitara™ products. He received his BSEE from Oklahoma State University in 1992, and MSEE and PhD from the University of Illinois Urbana-Champaign in 1993 and 1996. He has been with TI since 1996 and was elected Fellow in 2016. He has held key design roles for 8 generations of technology drivers with TI’s DSP and Processor business groups.