Highly Energy‐Efficient Processing and Machine Learning for Sensor Data Sensemaking: Building the Next‐Generation Internet of Things
Massimo Alioto, National University of Singapore
ABSTRACT: The Internet of Things (IoT) is now taking off as new technology wave in the semiconductor industry. The IoT is currently posing several challenges at its edge, in view of the strict requirements in terms of miniaturization, cost and lifetime of the distributed sensors (“IoT nodes”) that constitute its physical interface. Being relatively incompressible, the large wireless power associated with radios is generally mitigated by making IoT nodes smarter, hence reducing communications with the cloud. To retain the advantages of pushing significant processing into the IoT nodes, ultra‐low energy processing needs to be achieved by leveraging multiple design dimensions, ranging from energy‐performance scaling (e.g., wide voltage scaling), to energy-quality scaling (e.g., adjustable accuracy), and application specific accelerators for data sensemaking (e.g., machine learning engines).
In this tutorial, a survey of fresh ideas and recent techniques to design ultra‐low energy circuits for in‐node processing in IoT applications is presented. A preliminary analysis of the current status of the IoT and trends in the foreseeable future are introduced to understand the system constraints, and translate them into design specifications. Then, minimum‐energy operation is discussed by introducing near‐threshold CMOS logic circuits along with their unique properties and challenges, while debunking several wrong assumptions stemming from traditional above‐threshold low‐power common wisdom. Practical design guidelines are also provided for near‐threshold standard cell libraries, clock networks, memories, and other aspects related to automated design. For the first time, a novel variation‐aware design framework is presented to quickly estimate the typically large design margin imposed by process/voltage/temperature variations, and guide the design to reduce the design margin.
As crucial building block of IoT nodes with on‐chip sensor data sensemaking, energy‐efficient accelerators for machine learning are introduced, building on the above circuit‐level techniques. Such accelerators introduce the ability to perform event detection and classification (e.g., vision, audio), thus enabling context awareness. The architectural implications of near‐threshold operation and system activation patterns are examined. As particularly important case, low-energy deep learning accelerators are discussed by highlighting the “big ideas” that are enabling the recent and very rapid improvements in energy efficiency. Adaptation is explored in terms of dynamic energy‐quality management under time‐varying accuracy targets. Concepts are exemplified by integrated prototypes from industry and academia.
(M’01–SM’07‐F’16) received the Laurea (MSc) degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively. He is with the Department of Electrical and Computer Engineering, National University of Singapore where he leads the Green IC group and is the Director of the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan Ann Arbor (2011‐2012), BWRC – University of California, Berkeley (2009‐2011), and EPFL (Switzerland, 2007).
He has authored or co‐authored more 250 publications on journals and conference proceedings. He is co‐author of three books, including the first book on integrated circuit and system design for the IoT (Enabling the Internet of Things ‐ from Circuits to Systems, Springer, 2017). His primary research interests include ultra‐low power and self‐powered systems, near‐threshold and widely-voltage scalable circuits, energy‐quality scalable integrated systems, data‐driven integrated systems and embedded machine learning, hardware‐level security, among the others.
In 2009‐2010 he was Distinguished Lecturer of the IEEE Circuits and Systems Society, for which he is/was also member of the Board of Governors (2015‐2020) and Chair of the “VLSI Systems and Applications” Technical Committee (2010‐2012). In the last five years, he has given 50+ invited talks in top universities and leading semiconductor companies. He serves as Associate Editor in Chief of the IEEE Transactions on VLSI Systems (2013‐2018), and Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2018). He served as Guest Editor of several IEEE journal special issues (TCAS‐I, TCAS‐II, JETCAS). He also serves or has served as Associate Editor of a number of IEEE and ACM journals. Prof. Alioto was Technical Program Chair (SOCC, ICECS, NEWCAS, VARI, ICM, PRIME) and Track Chair in numerous conferences (ICCD, ISCAS, ICECS, VLSI‐SoC, APCCAS, ICM). Prof. Alioto is an IEEE Fellow.